• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    Method for producing a microelectronic device comprising: a) forming on an insulating layer of a semiconductor-on-insulator substrate, a first semiconductor block (12a) covered with a first constraint zone (21) adapted to induce a compressive stress in said first block and a second semiconductor block (12b) covered with a second stress zone (22) adapted to induce a voltage stress in said second block, the first block and the second block being each formed of a lower region (13a, 13b) based on amorphous semiconductor material, covered with an upper region of crystalline semiconductor material (14a, 14b) in contact with one of said stress zones, b ) re-crystallizing said lower region (13a, 13b) of said first block and said second block by serving as said upper region (14a, 14b) of crystalline material as starting area at a front of r ecristallisation.
    公开号:FR3015769A1
    申请号:FR1363418
    申请日:2013-12-23
    公开日:2015-06-26
    发明作者:Shay Reboh；Perrine Batude；Sylvain Maitrejean；Frederic Mazen
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD AND PRIOR ART This description relates to the field of structures formed of a semiconductor-on-insulator type substrate. and more particularly that of devices having a semiconductor-on-insulator type substrate on which several semiconductor zones having different mechanical stresses or undergoing different deformations are formed. By mechanical deformation is meant a material which has its parameter (s) elongated crystal (s) or shortened (s). In the case where the deformed mesh parameter is larger than the so-called "natural" parameter of the crystalline material, it is said to be in tensive deformation or in tension. When the deformed mesh parameter is smaller than the natural mesh parameter, the material is said to be compressive deformation or compression.
    [0002] To these states of mechanical deformation, one associates states of mechanical stresses. However, it is also common to refer to these deformation states as mechanical stress states. In the remainder of the present application, this notion of strain ("strain" in the English terminology) will be generically referred to as "constraint".
    [0003] For certain applications, in particular for producing transistors, it may be advantageous to provide a layer of constrained semiconductor material. A voltage or compression stress on a semiconductor layer makes it possible to induce an increase in the speed of the charge carriers, thus improving the performance of transistor devices formed in such a layer.
    [0004] A semiconductor-on-insulator substrate is commonly formed of a support layer covered by, and in contact with, an insulating layer, itself covered by, and in contact with, a semiconducting surface layer generally intended for serve as active layer that is to say in which at least a portion of electronic components such as transistors is intended to be formed. It is known to produce insulating semiconductor-type substrates in which the material of the semiconductive surface layer resting on the insulating layer is based on a constrained material. It is known, for example, to make substrates of the sS01 (strained silicon on insulator) type having a surface tension-doped silicon layer in the plane in which N-type transistors having improved performance can be formed. . Such a constraint is, however, unfavorable for P-type transistors. It is also known to make devices in which, on the same support, one or more transistors are voltage-stressed while one or more transistors are constrained in compression. Document US 2012/00682671 A1 for example provides a method in which a voltage-constrained NMOS transistor is formed and a PMOS-type transistor constrained in compression on the same substrate.
    [0005] In this method, to form a voltage-constrained semiconductor block, a SiGe zone is formed on an Si on insulator block, which is rendered amorphous by a lower region which is then recrystallized. During the recrystallization, the SiGe imposes its mesh parameter on Si in order to form a voltage-constrained semiconductor block intended to form a channel of an N-type transistor. Another block of Si intended to form a channel of a P type transistor is constrained in compression by means of enrichment in Germanium. Such a method has the disadvantage of being limited to the stress-stressing of Si and to the compressive stressing of SiGe, and to require for this purpose a SiGe growth which can be at once expensive and difficult to implement.
    [0006] Moreover, such a method requires many steps and in particular to have to use different methods to perform stress stressing and compressive stressing. There is the problem of finding a new method for the implementation, on the same substrate, of semiconductor zones having different constraints and which does not have the drawbacks mentioned above. DISCLOSURE OF THE INVENTION The present invention firstly relates to a method for producing a semiconductor structure comprising the steps of: a) forming on a layer based on amorphous material, a first semiconductor block covered with a first stress zone based on a voltage-constrained amorphous material adapted to induce a first state of stress in said first block and a second semiconductor block covered with a second stress zone based on an amorphous material constrained in compression adapted to induce a second state of stress in said second block, the first block being formed of a lower region based on amorphous semiconductor material, covered with an upper region of crystalline semiconductor material in contact with said first stress zone, the second block being formed of a lower region based on amorphous semiconductor material, covered with a r upper region of crystalline semiconductor material in contact with the second stress zone, b) recrystallizing the lower region of the first block and the lower region of the second block by serving as the upper region of crystalline material as starting area at a front of recrystallization. The layer of amorphous material on which the first block and the second block are formed, can be an insulating layer of a semiconductor-on-insulator substrate. The upper regions of crystalline semiconductor material of the first block and the second block which are not rendered amorphous are, by their proximity to the stress zones, those of the semiconductor blocks in which the deformations in the plane are the most important. . These constrained crystalline regions are used as starting seeds to recrystallize the lower regions of the semiconductor blocks in order to impose the mesh parameter from the upper regions to the lower regions and thus to create permanent elastic deformation in the lower regions. We can then remove the stress zones. An amorphous constraint material for forming the first stress zone and the second stress zone makes it possible to constrain various types of semiconductor materials, such as, for example, Si, Ge, SiGe, and GaAs lnP. The use of an amorphous material also makes it possible to achieve zones of stress of large thickness and which is not limited by phenomena of plastic relaxation as with a crystalline material. This therefore makes it possible to have a higher volume ratio between the stress zone and the constrained semiconductor block, thus a better transfer of stresses or deformations of the constrained zone towards the semiconductor block. Such a method may also make it possible to carry out the recrystallization and stressing of the first block and the second block at the same time or simultaneously. The first state of stress of the first semiconductor block may be a state of stress in compression, while the second state of stress of the second semiconductor block may be a state of stress in tension. The first block and said second block formed in step a) may advantageously be based on the same semiconductor material. This semiconductor material may for example be Si or Ge. Thus, with a process according to the invention, semiconductor blocks of material may be formed under constraints of different types, while limiting the number of stages and the cost of the process.
    [0007] The amorphous constrained material may advantageously be based on silicon nitride, or titanium nitride, or carbon. Such a method also makes it possible to limit the number of growth steps by epitaxy.
    [0008] According to a particular implementation of the process, at least one thermal anneal is carried out between step a) and step b) at a temperature below the recrystallization temperature of the amorphous semiconductor material and adapted to enable on stress of the non-amorphized crystalline upper region of the semiconductor block prior to recrystallization of amorphous red regions.
    [0009] With the aid of such annealing, the level of deformation in the semiconductor blocks can be further modified. According to a particular aspect of the method, the amorphization of said lower region of said first block can be carried out simultaneously or at the same time as that of said second block.
    [0010] According to a first implementation possibility, step a) may comprise at least one amorphizing ion implantation of said lower region of said first block and said second block. This implantation is then performed so as to maintain the crystal structure of said upper region of said first block and said second block.
    [0011] According to a second possible embodiment, step a) may comprise an etching of a stack formed of a layer of crystalline semiconductor material resting on a layer of amorphous semiconductor material. This stack may have been previously formed by: - producing a layer of amorphous semiconductor material on a layer of crystalline material of a first substrate, - bonding of said layer of amorphous semiconductor material on a superficial insulating layer covering a second substrate. After bonding, a thickness of the first substrate can be removed.
    [0012] The layer of amorphous semiconductor material on the first substrate can be made by deposition or amorphous ion implantation of a layer of crystalline semiconductor material. The production of said first stress zone and / or the second stress zone may comprise steps of: depositing a layer of constrained material on said first block and on said second block, forming a masking covering a given block among the first block and the second block covered by the constrained material, an opening of the masking revealing the other block among the first and the second block, etching of this other block through the opening of the masking. According to an alternative embodiment of the method wherein said substrate is a voltage-insulator-type semiconductor substrate, the first state of stress in said first block may be such that the first block is relaxed or constrained in compression while that the second state of stress in said second block is such that the second block is stress-stressed. The present invention also relates to a semiconductor structure formed of a substrate comprising a support layer, an insulating layer resting on the support layer and on and in contact with the insulating layer, a first semiconductor block constrained in compression in the plane or relaxed and a second semiconductor block constrained in tension in the plane, the first semiconductor block and the second semiconductor block being and based on the same semiconductor material. The first block and the second block can belong to the same layer. Alternatively, the first block and the second block may be disjoint. The present invention further provides a microelectronic device comprising a semiconductor structure as defined above with at least one channel of a P-type transistor formed in the first semiconductor block and at least one channel of a transistor. N-type formed in the second semiconductor block.
    [0013] BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIGS. 1A-1G and 5A-5B illustrate an example of a method according to the invention, for forming a semiconductor-on-insulator-type substrate having on the surface of constrained semiconductor blocks based on the same semiconductor material and resting on the insulating layer of the substrate, one or more first (s) block (s) being constrained (s) in tension, while one or more second (s) block (s) are constrained (s) in compression, or relaxed stresses; FIGS. 2A-2B illustrate an alternative embodiment in which the lower part of semiconductor blocks arranged on a semiconductor-on-insulator substrate is amorphized, then stressing zones are formed to induce a stress in these blocks, before recrystallizing the lower part of the blocks in order to perform a transfer of the deformed mesh parameter in the plane of a non-amorphized upper part of the blocks; FIGS. 3A-3B illustrate another variant in which different zones of stress are formed on the same superficial semiconductor layer of a semiconductor-on-insulator substrate; FIGS. 4A-4G illustrate another variant in which a layer of amorphous semiconductor material is produced on a layer of crystalline semiconductor material which is adhered to an insulating layer in order to form a semiconductor-type substrate on insulator whose superficial semiconductor layer is formed of a lower sub-layer based on amorphous semiconductor material and an upper sub-layer based on crystalline semiconductor material; FIG. 6 illustrates a transistor device formed using a method according to the invention, with a P type transistor formed in a first semiconductor block constrained in compression and an N type transistor formed in a second semiconductor block constrained in tension; FIGS. 7A-7E illustrate another alternative embodiment making it possible to form, from a substrate of semiconductor type constrained on an insulator, a semiconductor block that is relaxed or constrained in compression and a semiconductor block constrained in tension. resting on the insulating layer of the substrate; As is customary in the representation of semiconductor structures, the various sectional views are not drawn to scale. The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable. In addition, in the following description, terms which depend on the orientation of the structure, such as "lower", "higher", apply considering that the structure is oriented as illustrated in the figures. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS A first example of a method according to the invention will now be described with reference to FIGS. 1A-1G and 5A-5B. The starting material of this process is a semiconductor-on-insulator type substrate, and can for example be of the SOI type (SOI for "silicon on insulator" or "silicon on insulator").
    [0014] The substrate 1 thus comprises a support layer 10, for example a semiconductor layer, which may be based on Si, and an insulating layer 11, for example based on silicon oxide, which is located on and in contact with the support layer 10. The insulating layer 11 may for example be BOX (BOX for "Burried Oxide") with a thickness (measured in a direction parallel to the z axis of an orthogonal reference [0; x; y z] given in FIG. 1A), for example between 10 nm and 100 nm. The substrate 1 further comprises a so-called "superficial" semiconductor layer 12 situated on and in contact with said insulating layer 11. This superficial semiconductor layer 12 may have a thickness for example of between 5 nm and 50 nm (FIG. ).
    [0015] Firstly, in the surface semiconductor layer 12, a plurality of etched blocks 12a, 12b are formed by using the insulating layer 11 as a barrier layer. The blocks 12a, 12b are intended to form one or more active zones for accommodating components or parts of components, for example transistors. The etching of the blocks 12a, 12b can be carried out for example with the aid of TMAH (for "Tetra methyl ammonium hydroxide", for example in the case where the blocks 12a, 12b are based on Silicon (Figure 1B). FIG. 1C), a first constraint zone 21, also called a "stress zone", is formed on a first semiconductor block 12a and intended to induce in the first semiconductor block 12a a first type of constraint, for example to constraining the first semiconductor block 12a in compression, while on a second semiconductor block 12b, a second stressing zone 22 also called "stress zone" is formed and intended to induce in the second semiconductor block 12b a second type of constraint, for example to force the second semiconductor block 12b in tension The first stress zone 21 may itself be based on an amorphous material having an intrinsic elastic stress ue while the second stress zone 22 is based on an amorphous material having an intrinsic elastic stress in compression.
    [0016] The stress exerted on the blocks 12a, 12b is not imposed here by a crystalline material having a mesh parameter different from that of the semiconductor material of the blocks 12a, 12b. The first stress zone 21 and the second stress zone 22 may be based on a constrained amorphous material such as, for example, silicon nitride, or titanium nitride, or DLC type carbon (DLC for "Diamond like Carbon ") or tetrahedral amorphous carbon (ta-C). An example of a method for producing the stress zones is given in FIGS. 5A-5B. The first stress zone 21 may be formed firstly by depositing a first layer 17 based on forced amorphous material made to cover the insulating layer 11 and the semiconductor blocks 12a, 12b. The first layer 17 may for example be based on voltage-strained SiXNV and adapted to induce on the first semiconductor block 12a a compressive stress. The first layer 17 may have a thickness for example between 10 nm and 200 nm and a nominal stress for example of the order of 2 GPa. Then, forming a first mask 31 covering the first block 12a and which has an opening revealing the second block 12b (Figure 5A). The first stress layer 17 is then etched through the opening (s) of the first mask 31 so as to maintain a stress zone 21 only on the first block 12a. The second stress zone 22 is then formed by depositing a second layer 19 based on forced amorphous material, for example based on Six, Ny, constrained in compression and adapted to induce on the second semiconductor block 12b a stress in tension. . The second stress layer 19 may have a thickness of, for example, between 10 nm and 200 nm and a nominal stress, for example of the order of 2 GPa. This deposit is made so as to cover the insulating layer 11 and the semiconductor block 12b. The second layer 19 based on strained amorphous material may also cover the first masking formed above the first block 12a. Then, forming a second mask 32 covering the second block 12b (Figure 5B). The second layer 19 is then etched through the opening (s) of the first mask 31 and the second mask 32 so as to keep a stress zone 22 only on the second block 12b and the stress zone 21 only on the first block 12a. Masks 31, 32 are then removed. Then (FIG. 1D), a so-called "buried" amorphization of the semiconductor blocks 12a, 12b is performed, so as to render amorphous regions 13a, 13b located in the lower part of the blocks 12a. , 12b respectively under other regions 14a and 14b located in the upper part of the blocks 12a, 12b whose crystal structure is preserved.
    [0017] The amorphous lower regions 13a, 13b of the blocks 12a, 12b may extend respectively under the crystalline regions 14a, 14b to the insulating layer 11 of the substrate 1, while the upper regions 14a, 14b whose crystalline structure has The amorphization of the regions 13a and 13b can be carried out by means of at least one ion implantation step, respectively, between the amorphous lower regions 13a, 13b and the stress zones 21, 22. In this embodiment, the amorphous implantation of the semiconductor material of the semiconductor regions 13a, 13b is carried out for example using Si or Ge, for example in a dose of between 1E14 and 1E15 and an energy between 2 keV and 100 keV. The amorphous regions 13a, 13b may have a thickness e1 for example between 50% and 95% of the total thickness e1 + e2 of the blocks 12a, 12b, while the crystalline regions 14a, 14b may have a thickness e2 comprised by example between 50% and 5% of the total thickness e1 + e2 of the blocks 12a, 12b (the thicknesses being measured in a direction parallel to the axis z of the reference [O, x, y, z] given in FIG. 1D ). By way of example, a block of Si with a thickness of 33 nm may have an amorphous region rendered between 70% and 80% of its lower thickness by ion implantation of Si + at an energy of 20 keV and a dose of 3.5 * 1014. atoms / cm2.
    [0018] The upper regions 14a, 14b whose crystalline structure has been preserved extend respectively between the lower regions 13a, 13b amorphous and the stress zones 21, 22. The stress zones 21, 22 arranged on and in contact with, respectively, the upper crystalline region 14a of the first block 12a and the upper crystalline region 14b of the second block 12b can induce a stress in the important plane in the material of these upper regions 14a, 14b. The regions 13a, 13b of the blocks 12a, 12b are then recrystallized (FIG. 1E).
    [0019] For this, at least one thermal annealing is carried out at a temperature for example between 450 ° C and 1300 ° C, according to a duration for example greater than Os and less than 1h. Vertical recrystallization fronts leading respectively from the crystalline upper regions 14a, 14b to the insulating layer 11 are thus created. Insofar as the lower regions 13a, 13b of the blocks 12a, 12b rest on an amorphous layer, it is the crystalline regions 14a, 14b, stressed respectively by the constraint zones 21 and 22, which impose their respective mesh parameter. to the lower regions 13a, 13b of the blocks 12a, 12b during recrystallization. The crystalline regions 14a, 14b thus impose a deformed mesh parameter in the plane to the underlying recrystallized regions 13a, 13b. Due to their proximity to the stress zones 21, 22, the crystalline regions 14a, 14b are those of the blocks 12a, 12b, which are subjected to the most important mesh parameter deformations. At the end of the recrystallization (FIG. 1F), blocks 12a, 12b respectively constrained in compression and in tension are thus obtained, the respective stresses of which are greater than those experienced just after the step of producing the stress zones. and 22 previously described in connection with Figure 1C. Then, the stress zones 21, 22 can be removed (FIG. 1G).
    [0020] The blocks 12a, 12b then retain respectively a compressive stress and a stress in tension. From the blocks 12a, 12b, it is then possible to form at least a first P-type transistor T1, for example of the PMOS or PFET type, the channel of which is provided in the first compression-clamped block 12a and at least one second T2 transistor. type N, for example of NMOS or NFET type, whose channel is provided in the second block 12b stressed in tension. The channels of transistors T1 and T2 are then made of the same semiconductor material, in this example of Si (FIG. 6). According to a variant of the example of the method which has just been described, after the amorphization step of the regions 13a, 13b of the blocks 12a, 12b and prior to the recrystallization annealing described in connection with FIG. prior to at least one annealing at a predicted temperature lower than the crystallization temperature of the semiconductor material of the blocks 12a, 12b. This annealing can be carried out at a temperature of, for example, between 280 ° C. and 400 ° C., for a duration of for example between 30 s and 5 h. One or more anneals prior to the recrystallization step can ultimately increase the stress induced in the blocks 12a, 12b. A device as illustrated in FIG. 1F comprising on and in contact with the insulating layer 11 of a semiconductor-on-insulator type substrate, a first semiconductor block 12a forced into compression and a second semiconductor block 12b. constrained in tension and based on the same semiconductor material as the first block, can be achieved by following a sequence of steps having an order different from that just given. For example, according to a variant (FIGS. 2A-2B) of the process which has just been described, it is possible to carry out the so-called buried amorphization step (FIG. 2A) before that consisting in forming the stress zones 21, 22 respectively on the regions 14a, 14b of the blocks 12a, 12b which have not been made amorphous and whose crystalline structure has thus been preserved (FIG. 2B). According to another variant (FIGS. 3A-3B) of the examples of the method which have just been given, it is possible to carry out the step of forming the zones 21, 22 of stress before that of etching of the semiconductor layer 12 of the substrate. Thus, the first stress zone 21 is formed on one zone of the superficial semiconductor layer 12 of the substrate, and the second stress zone 22 on another zone of this superficial semiconductor layer 12 (FIG. 3A).
    [0021] Then, etching of the superficial semiconductor layer 12 of the substrate between the stress zones 21 and 22, so as to form the disjoint semiconductor blocks 12a, 12b resting on the insulating layer 11 of the substrate (FIG. 3B). . The etching can be performed for example using TMAH when the layer 12 is based on Si.
    [0022] According to another exemplary embodiment given in FIGS. 4A-4G, the amorphized regions 13a, 13b of the semiconductor blocks 12a, 12b can be produced before the step of delimiting these blocks by etching of the superficial semiconductor layer. 12 of a substrate.
    [0023] Thus, firstly, on a support 100, for example a bulk substrate based on crystalline Si ("bulk" according to the English terminology), a layer of amorphous semiconductor material 103, in particular a layer of If amorphous (Figure 4A). This layer of amorphous semiconductor material 103 can be made by amorphization, for example by ion implantation of a surface layer of the substrate 100, or by depositing a layer of amorphous semiconductor material on the substrate 100. amorphous semiconductor material 103 may have a thickness e1 (measured in a direction parallel to the z axis) of the orthogonal reference [0; x; y; z] given in FIG. 4A, for example between 5 nm and 200 nm. nm. Subsequently, an embrittlement zone 105 is formed in the substrate 100, for example by carrying out hydrogen implantation as implemented in a method of the type commonly known as smart cutTM. Implantation is performed at a depth H (measured in a direction parallel to the axis z in Figure 4B from an upper face also called the front face of the substrate 100 which is carried out) greater than the thickness e1 of the layer of amorphous semiconductor material , so as to maintain a layer of intact crystalline semiconductor material 104 of non-zero thickness between the amorphous layer 103 and the embrittlement zone 105.
    [0024] The layer of amorphous semiconductor material 103 of the substrate 100 is then bonded (FIG. 4C) with a superficial insulating layer 201, for example based on SiO 2, of another substrate 200. This bonding is preferably carried out at a chosen temperature. less than a given threshold, which depends in particular on the type of amorphous semiconductor material 103, so as to prevent recrystallization of this semiconductor material 103. The temperature at which the bonding is carried out may for example be chosen to be less than 500. ° C. An annealing is then carried out at a temperature below said given threshold, for example 500 ° C., and the substrate 100 is fractured at its weakening zone 105, so as to retain only the semiconductor layer 104 of the substrate 100 in contact with the layer of amorphous semiconductor material 103, the remainder of the substrate 100 being removed (FIG. 4D). A planarization step, for example by mechano-chemical polishing (CMP) may then be performed to reduce the thickness of the semiconductor layer 104. Next, 112a, 112b disjoint blocks are formed by etching the layer of semi material crystalline conductor 104 and the layer of amorphous material 103 until it reaches the insulating layer 201 (FIG. 4E). On a first semiconductor block 112a, a first constrained area 121 is formed, for example based on voltage-constrained silicon nitride, adapted to induce a compressive stress in this first block 112a, while on a second block 112b, forming a second stress zone, for example based on compression-constrained silicon nitride, adapted to induce a voltage stress in the second block 112b (FIG. 4F).
    [0025] Subsequently, recrystallization of regions of amorphous semiconductor material 103 of the blocks 112a, 112b is performed using areas of the crystalline semiconductor material layer 104 as the starting area of a recrystallization front. Recrystallization of the blocks 112a, 112b also makes it possible to transfer the mesh parameter from their upper portion based on crystalline semiconductor material undergoing stress exerted by the zones 121, 122, towards their lower part (FIG. 4G). A method as implemented according to the invention is not limited to the stressing of silicon blocks and can be applied to other semiconductor materials such as Ge, SixGel, InP, GaAs.
    [0026] A method as described above with reference to FIGS. 1A-1G can also be implemented using a semiconductor substrate forced on insulator 300 (FIG. 7A), in particular of the type sS01 (for "strained silicon"). It is "insulator" or "constrained silicon on insulator") having a Si-based surface semiconductor layer 312 which is stressed, for example in tension, and located on and in contact with the insulating layer 11 of the substrate 300. in the superficial semiconductor layer 312, a first block 312a and a second block 312b (FIG. 7B) are stressed, then a first stress zone 21 is produced on the first semiconductor block 312a while on the second semiconductor block 312b, a second stress zone 22 is formed (Figure 7C). The first stress zone 21 may be formed of amorphous material such as for example SixNy, having an intrinsic voltage stress tending to oppose the initial voltage stress of the first block 312a.
    [0027] The second stress zone 22 may, for its part, be formed of amorphous material constrained in compression such as for example SixNy. The second constraint zone 22 may thus make it possible to increase the initial stress of the second block 312b. Subsequently, a buried amorphization step of the semiconductor blocks 312a, 312b (FIG. 7D) is performed, so as to render the lower regions 313a, 313b of the blocks 312a, 312b amorphous respectively below the other regions 314a, 314b. blocks 312a, 312b and whose crystalline structure is preserved. The semiconductor blocks 312a, 312b are then recrystallized. During this recrystallization, the upper regions 314a, 314b of the blocks 312a, 312b which are situated directly under the stress zones 21 and 22 impose their mesh parameter on the lower regions 313a, 313b. It is thus possible, after recrystallization, to obtain a semi-conductor structure in which the second semiconductor block 312b is stressed in tension and in which the first semiconductor block 312a is relaxed or constrained in compression, particularly as a function of the intrinsic stress level. of the material of the first stress zone 21, and therefore of the initial state of stress of the first semiconductor block 312a before amorphization. According to another variant of one or the other of the examples of the process which have just been described, it is possible to carry out amorphization steps of the first block and the second semiconductor block, and then to recrystallize said lower region of the first block and said second block by serving as said top region of crystalline material as starting area at a recrystallization front, without performing etching of the layer in which these blocks are located.
    权利要求:
    Claims (12)
    [0001]
    REVENDICATIONS1. A method of producing a semiconductor structure comprising the steps of: a) forming on an insulating layer of a semiconductor-on-insulator substrate a first semiconductor block (12a, 112a) covered with a first stress zone (21, 121) based on a voltage-strained amorphous material adapted to induce a first state of stress in said first block and a second semiconductor block (12b, 112b) covered with a second zone of stress stress (22, 122) based on an amorphous material constrained in compression adapted to induce a second state of stress in said second block, the first block and the second block being each formed of a lower region (13a, 13b, 103 ) based on amorphous semiconductor material, covered with an upper region of crystalline semiconductor material (14a, 14b, 104) in contact with one of said stress zones, b) recrystallizing said lower region (13a, 13b, 10) 3) of said first block and said second block by serving as said top region (14a, 14b, 104) of crystalline material as a starting zone at a recrystallization front.
    [0002]
    2. Method according to claim 1, wherein step a) is carried out by an amorphous implantation of the lower region (13a, 13b, 103) of the first block and the second block, said implantation being carried out so as to preserve the structure crystalline of said upper region (14a, 14b, 104).
    [0003]
    The method of claim 1, wherein step a) comprises etching a stack formed of a layer of crystalline semiconductor material (104) resting on a layer of amorphous semiconductor material (103).
    [0004]
    The method according to claim 3, wherein said stack is previously formed by steps of: - performing, by amorphous deposition or implantation, a layer of amorphous semiconductor material (103) on a layer of crystalline material (104) ) of a first substrate (100), - bonding said layer of amorphous semiconductor material (103) to a surface insulating layer (202) covering a second substrate (200).
    [0005]
    5. Method according to one of claims 1 to 4, wherein said amorphous stress material is based on SiXNV or TiN or carbon.
    [0006]
    6. Method according to one of claims 1 to 5, wherein the realization of the first stress zone and / or the second stress zone comprises steps of: - depositing a layer of constrained material on said first block and on said second block, - formation of a masking covering a given block among the first block and the second block, an opening of said masking revealing another block among the first block and the second block, - etching of the other block to through the opening of the masking.
    [0007]
    7. Method according to one of claims 1 to 6, wherein the first block and said second block are based on the same semiconductor material.
    [0008]
    8. Method according to one of claims 1 to 7, the first state of stress in the first semiconductor block being such that the first semiconductor block is constrained in compression the second state of stress in said second block being such that the second block is semiconductor is strained in tension.
    [0009]
    9. Method according to one of claims 1 to 8, wherein said substrate is a voltage-insulator-type semiconductor substrate, the first state of stress in said first block being such that the first block is relaxed the second state. stress in said second block being such that the second block is stressed in tension.
    [0010]
    10. Method according to one of claims 1 to 9, further comprising, between step a) and step b), at least one thermal annealing performed at a temperature below the recrystallization temperature of the semiconductor material. amorphous.
    [0011]
    11. A semiconductor structure formed of a substrate of a type comprising a support layer, an insulating layer resting on the support layer and on and in contact with the insulating layer, a first semiconductor block constrained in compression or relaxed and a second semiconductor block stressed in tension, the first semiconductor block and the second semiconductor block being based on the same semiconductor material.
    [0012]
    A microelectronic device comprising a structure according to claim 11, wherein at least one channel of a P-type transistor is formed in the first semiconductor block, at least one channel of an N-type transistor being formed in the second semiconductor block.
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    同族专利:
    公开号 | 公开日
    EP2887384B1|2022-02-09|
    US20150179665A1|2015-06-25|
    FR3015769B1|2017-08-11|
    US9761607B2|2017-09-12|
    EP2887384A1|2015-06-24|
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    FR3033081B1|2015-02-24|2017-03-31|Commissariat Energie Atomique|METHOD FOR MODIFYING THE STRAIN STATUS OF A SEMICONDUCTOR STRUCTURE WITH TRANSISTOR CHANNEL STAGES|
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    FR3051970B1|2016-05-25|2020-06-12|Commissariat A L'energie Atomique Et Aux Energies Alternatives|REALIZATION OF A CHANNEL STRUCTURE FORMED OF A PLURALITY OF CONSTRAINED SEMICONDUCTOR BARS|
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    FR3091619B1|2019-01-07|2021-01-29|Commissariat Energie Atomique|Healing process before transfer of a semiconductor layer|
    法律状态:
    2015-12-31| PLFP| Fee payment|Year of fee payment: 3 |
    2016-12-29| PLFP| Fee payment|Year of fee payment: 4 |
    2018-01-02| PLFP| Fee payment|Year of fee payment: 5 |
    2019-12-30| PLFP| Fee payment|Year of fee payment: 7 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 8 |
    2021-12-31| PLFP| Fee payment|Year of fee payment: 9 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1363418A|FR3015769B1|2013-12-23|2013-12-23|IMPROVED METHOD FOR PRODUCING CONCEALED SEMICONDUCTOR BLOCKS ON THE INSULATING LAYER OF A SEMICONDUCTOR SUBSTRATE ON INSULATION|FR1363418A| FR3015769B1|2013-12-23|2013-12-23|IMPROVED METHOD FOR PRODUCING CONCEALED SEMICONDUCTOR BLOCKS ON THE INSULATING LAYER OF A SEMICONDUCTOR SUBSTRATE ON INSULATION|
    EP14199888.0A| EP2887384B1|2013-12-23|2014-12-22|Improved method for producing stressed semiconductor blocks on the insulating layer of a semiconductor on insulator substrate|
    US14/579,069| US9761607B2|2013-12-23|2014-12-22|Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate|
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